? semiconductor components industries, llc, 2001 october, 2001 rev. 8 1 publication order number: sn74ls273/d sn74ls273 octal d flip-flop with clear the sn74ls273 is a high-speed 8-bit register. the register consists of eight d-type flip-flops with a common clock and an asynchronous active low master reset. this device is supplied in a 20-pin package featuring 0.3 inch lead spacing. ? 8-bit high speed register ? parallel register ? common clock and master reset ? input clamp diodes limit high-speed termination effects guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky http://onsemi.com pdip20 n suffix case 738 20 1 20 1 a = assembly location wl = wafer lot yy = year ww = work week sn74ls273n awlyyww marking diagrams ls273 awlyyww soic20 dw suffix case 751d 1 1 20 1 soeiaj20 m suffix case 967 74ls273 awlyww 1 device package shipping ordering information sn74ls273n pdip20 1440 units/box sn74ls273dw soicwide 38 units/rail sn74ls273dwr2 soicwide 2500/tape & reel sn74ls273m see note 1. soeiaj20 sn74ls273mel see note 1. soeiaj20 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative.
sn74ls273 http://onsemi.com 2 18 17 16 15 14 13 1234 56 7 20 19 8 v cc mr q 7 d 7 d 6 q 6 d 5 q 5 d 4 q 0 d 0 d 1 q 1 q 2 d 2 d 3 910 q 3 gnd 12 11 q 4 cp connection diagram dip (top view) clock (active high going edge) input data inputs master reset (active low) input register outputs cp d 0 - d 7 mr q 0 - q 7 0.5 u.l. 0.5 u.l. 0.5 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names truth table mr cp d x q x l x x l h h h h l l h = high logic level l = low logic level x = immaterial logic diagram cp mr d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 cp d cd q cp d cd q cp d cd q cp d cd q cp d cd q cp d cd q cp d cd q cp d cd q 14 1 26 7 3 8 4 5 9 11 12 13 15 v cc = pin 20 gnd = pin 10 = pin numbers 17 18 16 19
sn74ls273 http://onsemi.com 3 functional description the sn74ls273 is an 8-bit parallel register with a common clock and common master reset. when the mr input is low, the q outputs are low, independent of the other inputs. information meeting the setup and hold time requirements of the d inputs is transferred to the q outputs on the low -to-high transition of the clock input. dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih in p ut high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 2.) 20 100 ma v cc = max i cc power supply current 27 ma v cc = max 2. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions f max maximum input clock frequency 30 40 mhz figure 1 t phl propagation delay, mr to q output 18 27 ns figure 2 t plh t phl propagation delay, clock to output 17 18 27 27 ns figure 1 ac setup requirements (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions t w pulse width, clock or clear 20 ns figure 1 t s data setup time 20 ns figure 1 t h hold time 5.0 ns figure 1 t rec recovery time 25 ns figure 2
sn74ls273 http://onsemi.com 4 1.3 v *the shaded areas indicate when the input is permitted to * change for predictable output performance. 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v cp d q n t s (h) t h (h) t s (l) t h (l) 1/f max t plh t plh t phl t phl mr cp q n q n 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t rec t phl t plh t w 1.3 v 1.3 v 1.3 v * t w figure 1. clock to output delays, clock pulse width, frequency, setup and hold times data to clock figure 2. master reset to output delay, master reset pulse width, and master reset recovery time ac waveforms definition of terms setup time (t s ) e is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low-to-high in order to be recognized and transferred to the outputs. hold time (t h ) e is defined as the minimum time following the clock transition from low-to-high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low-to-high and still be recognized. recovery time (t rec ) e is defined as the minimum time required between the end of the reset pulse and the clock transition from low-to-high in order to recognize and transfer high data to the q outputs.
sn74ls273 http://onsemi.com 5 package dimensions n suffix plastic package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc
sn74ls273 http://onsemi.com 6 package dimensions d suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
sn74ls273 http://onsemi.com 7 package dimensions m suffix soeiaj package case 96701 issue o dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 12.35 12.80 0.486 0.504 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.81 --- 0.032 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). h e a 1 l e q 1 c a z d e 20 110 11 b m 0.13 (0.005) e 0.10 (0.004) view p detail p m l a b c d e e l m z
sn74ls273 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls273/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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